PLC Workshop 2014

Programming Models, Languages and Compilers Workshop for Manycore and Heterogeneous Architectures

Arizona Grand Resort

Phoenix, Arizona, USA, May 19th, 2014

Co-located with 28th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2014)

Call for Papers  
Important Dates
Submission Guide
Technical Program

Call for Papers

Three essential pillars to successful parallel computing - Productivity, Portability, Performance. Creating software for heterogeneous systems can be quite complex especially when the low-level details need to be managed and abstracted from the programmer. Emerging standards are providing an incremental development to target heterogeneous architectures, be it NVIDIA, ARM, Intel or AMD. We all know software is an expensive investment. Portability is necessary, ensuring long lifetime of the software and thus reducing the maintenance cost. Other challenges include locality and memory issues, load balancing, hiding latency with concurrency and so on.
This workshop aims to brainstorm ways to make programming heterogeneous systems less challenging and more interesting. We believe that this workshop will provide a forum for the presentation and discussions of research on all aspects of heterogeneous systems programming models, compiler optimizations, language extensions, and software tools for such systems.

Areas of interest include but are not limited to the following topics:

  • Multicore processors, Heterogeneous systems, Accelerators
  • Programming models: thread and task based models, data parallel models, stream programming
  • Programming environments for heterogeneous systems
    • OpenMP for Accelerator
    • OpenACC
    • OpenCL/CUDA
    • OpenHMPP and other related models
    • DSL
  • Compiler optimizations and tuning heterogeneous systems
    • Parallelization and loop transformations
    • Locality optimizations
    • SIMDization/Vectorization
    • Reducing synchronization and scheduling overheads on heterogeneous systems
    • Tiling, parametric tiling and offloading
  • Runtime systems for multicore processors, heterogeneous systems, accelerators
  • Debuggers, and performance analysis tools for heterogeneous system and accelerators
  • Application and Benchmarks

Important Dates:

  • Paper Submission Deadline: Jan 21st, 2014 (new deadline)
  • Paper Acceptance Notification: Feb 28th, 2014
  • Camera Ready Due: March 14th, 2014 March 21st, 2014
  • Workshop Date: May 19th, 2014

Submission Guidelines

Papers should present original research and should provide sufficient background material to make them accessible to the broader community. In addition, we solicit papers from practitioners describing problems and experiences building software tools for Multicore processors and GPU accelerators.

Full paper submissions should not exceed 10 pages in standard IEEE conference format. Submissions can be made through EDAS ( .

The proceedings of this workshop will be published electronically together with IPDPS proceedings via the IEEE Xplore Digital Library.

Selected papers will appear in the special issue of a Journal (TBD).


General Chair:

Steering Committee:

  • Guang R. Gao, University of Delaware, US
  • Xinmin Tian, Intel, US
  • Wenguang Chen, Tsinghua Universityi, China
  • Michael Wong IBM,Canada

Program Co-Chair:

  • Bronis R. De Supinski, Lawrence Livermore National Lab, US
  • Yonghong Yan (, University of Houston, US

Program committee:

  • Matthias Muller, TU Dresden, Germany
  • Pavan Balaji, Argonne National Laboratory, US
  • Sunita Chandrasekaran, University of Houston, US
  • James Beyer, Cray Inc, US
  • Yong Chen, Texas Tech University, US
  • Karine Heydemann, University of Pierre et Marie Curie, France
  • Xinmin Tian, Intel, US
  • Eric Stotzer, Texas Instruments, US
  • Chunhua Liao, Lawrence Livermore National Laboratory, US
  • Yuan Lin, NVIDIA, US
  • John Lidel, Cray, US
  • Markus Levy, Multicore Association, US
  • Wu-chun Feng, Virginia Tech, US
  • Stephen Olivier, Sandia National Laboratories, US